Multi-chip Integration

Thermal Perspective Design and Analysis of Multi-Stacked Structures

This paper investigates the thermal performance of multi-layer metal interconnects in three-dimensional (3D) stacked structures through finite element analysis (FEA). The 3D integrated circuit (3D IC) consists of five vertically stacked chips. The interconnections between the chips are achieved through through-silicon vias (TSVs), metal redistribution layers (RDLs), and hybrid bonding. Due to the complexity of the 3D IC structure, this work simplifies the detailed 3D IC model by employing equivalent models for each chip layer and the hybrid bonding structure. The study reveals that the portion of Cu significantly affects the thermal conductivity of the hybrid bonding structure, exhibiting quasi-linear dependence. Additionally, the misalignment between the upper and lower Cu pads decreases the thermal conductivity of the structure. Furthermore, equivalent models for different chip layers, including metal interconnect layers and TSVs, are constructed based on specific cases, and the equivalent thermal conductivities are extracted accordingly. Based on the equivalent results of each layer, the thermal conductivity of the complex 3D IC structure is ultimately determined. This work provides valuable results and guidance for the thermal design and practice of 3D IC.